x86/mm: fix #GP(0) in switch_cr3_cr4()
authorJan Beulich <jbeulich@suse.com>
Tue, 5 Mar 2019 16:02:36 +0000 (17:02 +0100)
committerJan Beulich <jbeulich@suse.com>
Tue, 5 Mar 2019 16:02:36 +0000 (17:02 +0100)
commitfdc2056767ba74346dfd8bbe868bb22521ba1418
tree346a6e28f526cae406e8923aa9e01551ed33ebbd
parent329b00e4d49f70185561d7cc4b076c77869888a0
x86/mm: fix #GP(0) in switch_cr3_cr4()

With "pcid=no-xpti" and opposite XPTI settings in two 64-bit PV domains
(achievable with one of "xpti=no-dom0" or "xpti=no-domu"), switching
from a PCID-disabled to a PCID-enabled 64-bit PV domain fails to set
CR4.PCIDE in time, as CR4.PGE would not be set in either (see
pv_fixup_guest_cr4(), in particular as used by write_ptbase()), and
hence the early CR4 write would be skipped.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Release-acked-by: Juergen Gross <jgross@suse.com>
xen/arch/x86/flushtlb.c